• Nenad Korolija School of Electrical Engineering, University of Belgrade
  • Vladisav Jelisavčić Mathematical Institute of the Serbian Academy of Sciences and Arts, Kneza Mihaila 36, 11001 Belgrade, Serbia
  • Zlatogor Minchev Institute of Information and Communication Technologies, Bulgarian Academy of Sciences, Sofia, Bulgaria
  • Veljko Milutinović Department of Computer Science, University of Indiana in Bloomington, Luddy Hall 2062, 700 N. Woodlawn Avenue Bloomington, IN 47408, Indiana, USA


high performance computing, dataflow architectures, control-flow architectures, job scheduling



High performance computing algorithms are often programmed solely for a single type of computer architecture. Some algorithms are more suitable for dataflow architectures, while others are scalable when executed using control-flow architectures. Increasing number of transistors on a single chip die creates the opportunity to combine multiple computing paradigms on a single chip. This allows faster communication between them and therefore faster algorithm execution.


This manuscript advocates for a hybrid control-flow and dataflow architecture on a single chip. Explanation of these architectures is followed by the design of the hybrid processor. The evaluation is based on the simulator of jobs executed on the proposed hybrid processor, dataflow architecture, and control-flow architecture.


Simulation comparison reveals the acceleration possibilities for certain high performance computing algorithms when executed using the proposed hybrid architecture. This can improve video surveillance in terms of better real-time face recognition, but also in terms of tracking subjects based on video streams from multiple locations, reducing the total power consumption at the same time.


The proposed computer architecture isn’t commercially available. However, with increasing number of transistors per chip, it is justified to combine existing computing paradigms in order to decrease the total processing time of high performance computing algorithms. Future work includes simulating the execution of an artificial intelligence algorithm that requires communication speed between dataflow and control-flow architectures comparable to the speed of modern cache memories to prevent under-utilization of a dataflow hardware.


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